As is known in the art, error correction and detection codes are used with data to correct errors which may occur in propagation of the data, or to at least detect the presence of an error in the propagated data. For example, a Reed-Solomon or Hamming code may be used to provide redundant bits to data. The data, with the redundant code, is fed through a portion of a system. When outputted from the system, the redundant code together with the data enables an error correction and detection (EDAC) process to reconstruct the data if one bit has been corrupted and to detect an error in the data if two bits have been corrupted. Such is sometimes known as SECDED, i.e., Single Error Correction/Double Error Detection.
As it is also known in the art, an extended EDAC is capable of correcting a nibble error (i.e., a four consecutive bit error). This is sometimes referred to in literature as “chipkill’: More particularly, in a memory system with 4 data width (i.e., nibble) memory chips, if one memory chip has read therefrom corrupted data, an extended EDAC is able to detect and correct the 4 bit (nibble) error from this chip.
As is also known in the art, one application for EDAC is with memory systems. One such system is described in U.S. Pat. No. 5,853,265 entitled ‘Memory Having Error Detection and Correction”, inventors John K. Walton and Christopher S. MacLellan, issued Sep. 14, 1999, assigned to the same assignees as the present invention. As described therein, a memory system includes a plurality of memory packages, or modules, for storing words. Each one of the packages is adapted to store a plurality of different bits of the word. The memory system includes an error detection and correction system adapted to detect an error produced in any one of the packages in storing the digital word. The memory system has a buffer for storing a digital word having N bits of data and M redundant bits for error detection and correction. As noted above, the redundant code together with the data enables an error correction and detection (EDAC) process to reconstruct the data if one bit or one nibble has been corrupted and to detect an error in the data if two bits have been corrupted.
As is also known in the art, many memory systems include a memory controller for providing read/write commands and address signals to a memory. The memory controller and servers making the read/write data request operate in response to system clock pulses. With a Double Data Rate (DDR) memory, in responses to a read command and address signals, the data read from the memory system, the read data, along with a read strobe pulse are produced asynchronously by the memory system. A synchronizer is provided to synchronize the asynchronous read data and read strobe to the system clock. One synchronizer used with such DDR memories is sometimes referred to as a PHY, such as, for example, a 0.11μ DDR2 PHY described in “0.11μ DDR2 PHY, November 2004, Technical Review Draft Nov. 18, 2004, TECHNICAL MANUAL” Copyright © 2004 by LSI Logic Corporation. As described therein, as each nibble of a data word is read from the memory in response to a read command, a read strobe is produced. The read strobes of the nibbles are compared with a time window providing an indication of whether the read strobes are provided within the expected time window after the read command. If the read strobes from all the read nibbles are produced within the expected time window, the data is accepted; otherwise an error is indicated and no read strobe is produced. With this arrangement, if one read strobe signal is missing, then no data is available on the PHY interface and hence there is no read strobe with which to latch the read data.